An Overview on Strategies to Perform VLSI Testing Productively Utilizing BIST

Abstract

A survey on techniques to perform VLSI Testing efficiently using BIST explores various methodologies to enhance Very Large-Scale Integration (VLSI) testing through Built-In-Self-Test (BIST) mechanism. The research delves into the significance of BIST controllers, such as the utilization of Low-Feedback Shift Registers (LFSR) for efficient testing. It also addresses the critical challenge of reducing test power in low-power VLSI circuits, emphasizing the need for innovative techniques to mitigate excessive power consumption during testing processes. Furthermore, the paper highlights the evolution of BIST applications in VLSI and System-on-Chip (SoC) testing, showcasing the growing importance of BIST for fault detection in modern electronic devices. Additionally, the study focuses on the design of Logic BIST structures, emphasizing the role of components like Test Pattern Generators, Response Analyzers, and Comparators in enhancing chip testing efficiency.