Power Integrity analysis and solution for PCIE-Gen5/6 Phy

Abstract

As the High-speed IO data rate is increasing, meeting the Power integrity specifications at the die, package & board is becoming highly challenging. With Data Centre servers, autonomous segment & desktop computing moving towards multiple PCIE5/6 PHY, it has become very critical to find the solution to meet the stringent noise spec with reduced BOM cost for all the segments of computing and also meet supply noise coupling requirements for multiple power management states of PHY. Power supply noise has been scaling to lower value to meet PSIJ (power supply induced Jitter) adding more complexity of the solution. Due to limitation of BOM cost, power & high-performance requirements, detailed understanding on source of power supply noise in the system has become necessary. This paper deals with the analysis & solution for power supply noise looking towards die, package & board with tightly integrated multiple ports of PCIE family.