A snapshot review on metal–semiconductor contact exploration for 7-nm CMOS technology and beyond

Abstract

Contact resistances take a significant portion of on-state resistances of advanced Si CMOS transistors. As a result, a metal–semiconductor contact resistivity (ρc) of sub-10–8 Ω cm2 or even sub-10–9 Ω·cm2 is required to achieve high performance for a very downscaled transistor. In this snapshot review on our ρc investigation efforts, we first introduce a test structure—a multiring circular transmission line model (MR-CTLM)—with high accuracy to measure ultralow ρc, and then we evaluate different contact solutions. Our contact solution exploration includes metal/insulator/semiconductor (MIS) contacts for n+-Si and advanced (gemano-)silicides for n+-Si and p+-SiGe. We will discuss limitations of MIS contacts. And we will demonstrate encouraging ρc of 10–9 Ω cm2 that meet the requirement of 7-nm or 5-nm CMOS technology nodes. Graphical abstract: [Figure not available: see fulltext.].