Image validation of parallel scanning tunneling microscopy with a CMOS MEMS probe array

Abstract

This paper reports on the design and test results from a dual-probe Scanning Tunneling Microscopy (STM) system, suitable for scaling to 1-D array parallel imaging with an eventual purpose for batch-nanofabrication. The 1-D array is fabricated using CMOS-MEMS technology. Each probe is individually addressable, equipped with an electrothermal (ET) microactuator for tip vertical deflection. A hierarchical dual servo system is tested to validate parallel STM operation with two probes on the chip. Dual STM images are obtained on a custom grating calibration sample. A second generation of probe array is being developed, where on-chip ET actuated micro-goniometers are designed for more scalable probe array-sample alignment.