A Self-Aligned Sacrificial Emitter Process for High Performance SiGe HBT in BiCMOS

Abstract

A self-aligned sacrificial emitter (SASE) process has been successfully developed in a BiCMOS technology. Selective epitaxy of SiGe originally developed for sub-100 nm CMOS nodes is used for a raised extrinsic base. Process integration includes building a sacrificial emitter pedestal using a CMOS gate-like etch, isolation of the emitter to extrinsic base by oxide CMP, and oxide recess etch to expose the emitter window for the in-situ doped emitter. Electrical results are shown to be comparable to hardware manufactured using other BiCMOS integration schemes. An intriguing growth mode of selective epitaxy has been found to have higher growth rate for high index planes.