Silicon nanowires are patterned down to 30 nm using complementary metal-oxide-semiconductor (CMOS) compatible process. The electrical conductivities of n-/p-leg nanowires are extracted with the variation of width. Using this structure, Seebeck coefficients are measured. The obtained maximum Seebeck coefficient values are 122 μV/K for p-leg and -94 μV/K for n-leg. The maximum attainable power factor is 0.74 mW/m K 2 at room temperature. © 2010 The Author(s).
CITATION STYLE
Jang, M., Park, Y., Jun, M., Hyun, Y., Choi, S. J., & Zyung, T. (2010). The Characteristics of Seebeck Coefficient in Silicon Nanowires Manufactured by CMOS Compatible Process. Nanoscale Research Letters, 5(10), 1654–1657. https://doi.org/10.1007/s11671-010-9690-2
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