Analysis of Leakage Power Reduction Techniques for Low Power VLSI Design

Abstract

Power dissipation has become one of the major concerns of VLSI circuit design with the rapid launching of battery operated applications. In high performance designs, the leakage component of power consumption is comparable to the switching component. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. In this paper, an 8X8 multiplier is designed using different leakage power reduction techniques like MTCMOS, DUAL-V t and LECTOR. All the above mentioned techniques are simulated using Cadence virtuoso tool in 90nm technology.