An efficient high speed GDI dadda multiplier

Abstract

In digital processing low-energy multipliers are our prime concern. We present energy minimization technique in this paper.To sieve out the futile switching power different approaches are exploited such as CMOS, PTL and GDI. In finite impulse response, convolution and other DSP applications multiplication occurs frequently. A good multiplier should provide good speed, low power and compact in a VLSI design. We propose a low PDP multiplier exploiting Dadda algorithm. Based on the proposed design PTL and GDI Dadda multipliers are designed and compared with conventional Dadda Multiplier. Tanner EDA has been used for design validation.