Multiple FPGA partitioning with performance optimization

Abstract

The problem of partitioning a technology mapped FPGA circuit onto multiple FPGAs of a specific target technology is addressed. Since the physical characteristics of the multiple FPGA system (MFS) pose added limits to the circuit partitioning algorithms, a rectilinear partitioning algorithm is presented, which efficiently and accurately handles timing specifications. The signal path delays are estimated via a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. A new dynamic net-weighing scheme is incorporated to minimize the number of pin-outs for each chip. Finally, a graph-based global router is developed for pin assignment, which handles the prerouted connections of the MFS structure.