A 1.8V P(SEUDO)SRAM using standard 140nm DRAM technology with self adapting clocked standby operation

Abstract

A pseudo static RAM (PSRAM) was fabricated using cost effective commodity DRAM 0.14μm technology. With the focus to mobile application the standby current was reduced by operating all the internal analog circuitries in a clocked arrangement with a duty cycle adaptively adjusted to the load. This principle was even proven for an on-chip bandgap cell (BGR) and a very efficient high voltage pump. The current consumption for all analog circuitries was 12μA@1.8V and together with the refresh portion less than 40μA@1.8V/25°C for a 32Mbit memory size to further approach towards low power SRAM substitution [1]. © 2006 IEEE.