Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments

Abstract

Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45 nm technology nodes to improve the transistor channel mobility and the electrical performance of logic devices. For 32 and 22 nm nodes, intense research work focuses on the integration and optimization of these different techniques by accumulating the effects of different stressors. Estimating the level and the distribution of the stress field generated in the channel by the fabrication process is a complex issue. The process simulation has a key role to play in order to face the many challenges associated with the stress engineering approach in terms of scalability, yield, and design. The objective of this paper is first to evaluate the stress distribution generated by the two most usual processing steps: contact etch stop liner and embedded SiGe stressors. Next, the final stress field in nanoscale device resulting of these intentional stress sources are evaluated. Process simulation has been able to quantify the global trend observed in relatively close correlation with several experimental studies.