Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction

Abstract

We investigated the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu–Esaki model of Fowler–Nordheim tunneling and direct tunneling current. Notably, the revised equations for both tunneling currents are proportional to V3, which originates from the linear dispersion of graphene. We developed a simulation tool by adopting revised tunneling equations using MATLAB. Thereafter, we optimized the device performance of the field-emission barristor by engineering the barrier height and thickness to improve the delay time, cut-off frequency, and power-delay product.