Design and Simulation of Pipelined Floating-Point Multiplier using Logisim

Abstract

Floating point multiplication is a cycle intensive operation used in signal and image processing. The operation time of multiplication could be increased by pipelining this process. In this paper, we design and simulate a pipelined floating-point multiplier using the Logisim simulation tool. The numbers are stored in the IEEE 754 single-precision format. This circuit can be implemented into newer microprocessors to be used as a fast multiplier. An array of these multipliers can be used in matrix multiplications in artificial neural networks and other applications where rapid multiplication is required. The Logisim simulation tool is used as it is easy to use and has a simple interface with powerful abstraction features. It is used in major universities to teach and simulate computer architecture.