Enhanced fault current-limiting circuit design for a DC fault in a modular multilevel converter-based high-voltage direct current system

Abstract

The main weakness of the half-bridge modular multilevel converter-based high-voltage direct current (MMC-HVDC) system lies in its immature solution to extremely high current under direct current (DC) line fault. The development of the direct current circuit breaker (DCCB) remains constrained in terms of interruption capacity and operation speed. Therefore, it is essential to limit fault current in the MMC-HVDC system. An enhanced fault current-limiting circuit (EFCLC) is proposed on the basis of fault current study to restrict fault current under DC pole-to-pole fault. Specifically, the EFCLC consists of fault current-limiting inductance LFCL and energy dissipation resistance RFCL in parallel with surge arrestor. LFCL reduces the fault current rising speed, together with arm inductance and smoothing reactor. However, in contrast to arm inductance and smoothing reactor, LFCL will be bypassed via parallel-connected thyristors after blocking converter to prevent the effect on fault interruption speed. RFCL shares the stress on energy absorption device (metal oxide arrester) to facilitate fault interruption. The DCCB requirement in interruption capacity and breaking speed can be satisfied effortlessly through the EFCLC. The working principle and parameter determination of the EFCLC are presented in detail, and its effectiveness is verified by simulation in RT-LAB and MATLAB software platforms.