Variable Body Biasing (VBB) based VLSI design approach to reduce static power

Abstract

The static power consumption is an important parameter concern in IC design due to t for a higher integration numbers of transistor to achieve greater performance in a single chip. Leakage current is the main issues for static power dissipation in standby mode as the size of transistor been scale. Therefore, the subthreshold leakage current rises due to threshold voltage scaling and gate leakage current increases due to scale down of oxide thickness. In this paper, a Variable Body Biasing (VBB) technique was applied to reduce static power consumption in VLSI design. The VBB technique used a DC bias at body terminal to control the threshold voltage efficiently. The Synopsys Custom Designer EDA tools in 90nm MOSFET technology was used to design a 1-bit full adder with VBB technique in full custom methodology. The simulation of 1-bit full adder was carried out with operation voltage VDD = 0.2V supply was compared in conventional technique and VBB technique. The results achieved the reduction in term of peak power, Ppeak = 33% and average power, Pavg = 13% in static CMOS 1-bit full adder compared with conventional bias and VBB technique.