New Algorithm for Dht and Its Verilog Implementation

Abstract

This paper presents a new algorithm for computing Discrete Hartley Transform (DHT) (type-2) of N with N=4r, where r>1.Paper also suggest VLSI architecture for the implementation of the newly developed algorithm. The computation of DHT using this algorithm is simple and requires less arithmetic operations compared with the general method for finding DHT. Also the suggested VLSI structure for the algorithm is regular and less complicated in terms of hardware requirement. Parallel processing of the algorithm make the processing further fast.