Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors

Abstract

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level performances to CMOS at comparable nodes. Analytical models of the parasitic capacitances of a TIGFET transistor were derived using techniques such as the equivalent Schwarz-Christoffel transformation and standard cylindrical capacitors and show close agreement with numerical simulations. The maximum capacitance of a TIGFET transistor is 2× larger than for a 15 nm CMOS High Performance (HP) device due to the TIGFET's two additional gated contacts, but this is countered by its ability for multiple modes of operation which reduces the effective switching capacitance per device. A TIGFET transistor sees, on average, only a 30% increase in total capacitance compared to a CMOS HP device. Additionally, the TIGFET's increased device functionality can be used to modify the circuit-level architecture of a TIGFET-based design to mitigate the performance impact of its larger device-level capacitance. This combination of a TIGFET's (1) multiple modes of operation, and (2) circuit-level architecture lead to enhanced system performance. In particular, we show that at the 15 nm technology node TIGFET technology has 18% lower energy-delay product for a fan-out of 4 and higher when using 1-bit full-adder logic circuit than for the equivalent node CMOS HP.