Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis

Abstract

Recently, a compact realization of logic gates using double-gate tunnel field effect transistors (DGTFETs) with independently-controlled gate has been proposed. The key elements in the proposed implementation are the suppression of the tunneling at the surface using gate-source overlap and enable tunneling inside the TFET body by choosing appropriate silicon body thickness. Though these implementations are compact, our study reveals that there are a few critical problems: high average subthreshold swing (SSavg), low ON-state current (ION) and large propagation delay (tpd). In this paper, we examine the root cause of these problems and explore solutions to tackle them. It is demonstrated that the techniques that boost the ION in a TFET do not necessarily increase the ION/IOFF ratio in the proposed implementations. The efficacy of these techniques in improving the ION/IOFF ratio depends on whether the gate-source overlap is able to suppress the tunneling at the surface and restrict the OFF-state current (IOFF). Furthermore, it is demonstrated that, for the AND functionality, compared to a purely silicon-based DGTFET (Si-TFET) employing silicongermanium heterojunction DGTFET (HJ-TFET) results in an increase in the ION by 143×, an increase in the ION/IOFF ratio by two orders of magnitude and an improvement in the SSavg by 45%, at VDD = 0.6 V. Moreover, a compact NAND gate realized using the proposed HJ-TFETs exhibits two orders of magnitude lower tpd, compared to the NAND gate realized using Si-TFET.