SDRAM delay fault modeling and performance testing

Abstract

DRAM timing parameter testing has always been considered a time-consuming process. This paper presents a systematic approach to analysis and classification of the synchronous DRAM (SDRAM) delay failure modes. Four delay fault models with March expression are proposed to cover important DRAM timing parameters. By at-speed March testing of these four types of delay faults, we can verify the DRAM timing specifications. ?? 2007 IEEE.