FPGA Accelerated Deep Learning for Industrial and Engineering Applications: Optimal Design Under Resource Constraints

Abstract

In response to the need for deploying the YOLOv4-Tiny model on resource-constrained Field-Programmable Gate Array (FPGA) platforms for rapid inference, this study proposes a general optimization acceleration strategy and method aimed at achieving fast inference for object detection networks. This approach centers on the synergistic effect of several key strategies: a refined resource management strategy that dynamically adjusts FPGA hardware resource allocation based on the network architecture; a dynamic dual-buffering strategy that maximizes the parallelism of data computation and transmission; an interface access latency pre-configuration strategy that effectively improves data throughput; and quantization operations for dynamic bit width tuning of model parameters and cached variables. Experimental results on the ZYNQ7020 platform demonstrate that this accelerator operates at a frequency of 200 MHz, achieving an average computing performance of 36.97 Giga Operations Per Second (GOPS) with an energy efficiency of 8.82 Giga Operations Per Second per Watt (GOPS/W). Testing with a metal surface defect dataset maintains an accuracy of approximately 90% per image, while reducing the inference delay per frame to 185 ms, representing a 52.2% improvement in inference speed. Compared to other FPGA accelerator designs, the accelerator design strategies and methods proposed in this study showcase significant enhancements in average computing performance, energy efficiency, and inference latency.