A hardware accelerator for context-Based adaptive binary arithmetic decoding in H.264/AVC1

Abstract

We propose a hardware accelerator for Contextbased Adaptive Binary Arithmetic decoding (CABAC) in H.264/AVC. We also propose an efficient memory system for easy integration with other components such as motion compensation and IDCT. We develop an efficient finite state machine so that our design can generate one bit every 2 to 3 clock cycles. Experimental result with FPGA prototyping shows that our design is sufficient to decode main profile CIF video stream at 30 fps.©2005 IEEE.