Electrospun Stacked Dual-Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Abstract

Thin-film transistors based on metal oxide semiconductors have become a mainstream technology for application in driving low-cost backplanes of active matrix liquid crystal displays. Although significant progress has been made in traditional marketable devices based on physical vapor deposition derived metal oxides, it has still been hindered by low yield and poor compatibility. Fortunately, developing solution-based 1D nanofiber networks to act as the fundamental building blocks for transistor has proven to be a simpler, higher-throughput approach. However, oxide transistors based on such princesses suffer from degraded carrier mobility and operational instability, preventing the ability of such devices from replacing present polycrystalline Si technologies. Herein, it is shown that double channel heterojunction transistors with high electron mobility (>40 cm2 V−1 s−1) and operational stability can be achieved from electrospun double channels composed of In2O3 and ZnO layers. Adjusting the stacking order and the stacking density of In2O3 and ZnO layers can effectively optimize the interface electron trap, leading to the formation of 2D electron gas and the reduction of stress-induced instability. These findings further elucidate the significant advance of electrospinning-derived double channel heterojunction transistors toward practical applications for future low-cost and high-performance electronics.