Implementation of High Speed Low Power Systolic Multiplier Based on Irreducible Trinomials

Abstract

This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.