Security, Stability, and Overhead: Configuration Design Study and Experimental Validation of XOR-ed Physical Unclonable Functions

Abstract

The rapid growth of resource-constrained Internet of Things (IoT) and edge devices necessitates lightweight, robust security solutions. Delay-based physical unclonable functions (PUFs), particularly xor arbiter PUFs (XOR APUFs), have emerged as promising alternatives due to their low hardware requirements and intrinsic security. However, traditional XOR APUFs face significant challenges in balancing reliability, security against modeling attacks, and hardware overhead. In this study, we explore new configurations of component-differential challenged XOR APUFs, a group of existing but underexplored PUFs that, we have found, hold promise for high performance in security, reliability, and overhead. Our study is focused on PUFs deployed on FPGAs, which are commonly used for reconfigurable computing/communication devices. Our FPGA-based experimental evaluations validate that our proposed PUFs achieve remarkable improvements in reliability and security, with minimal hardware overhead. Moreover, we outline the practical applicability of CDC-XOR PUFs in critical contemporary scenarios, including secure authentication for edge-AI devices, secure client enrollment in federated learning setups, and robust device management within industrial IoT (IIoT) environments. By effectively addressing the critical security-performance tradeoff, our proposed approach provides a compelling and scalable authentication solution well-suited for broad integration in modern IoT and edge computing ecosystems.