Simulation Study of the Instability Induced by the Variation of Grain Boundary Width and Trap Density in Gate-All-Around Polysilicon Transistor

Abstract

A macaroni type gate-all-around polysilicon transistor with a single grain boundary (GB) is precisely simulated to elucidate the impacts of the variation of GB width (WGB) and trap density (Dt) on its transfer characteristics. At the weak inversion region, the shift of the threshold voltage and subthreshold swing caused by GB are almost determined by the total number of the trap state in the GB (∝ WGB × Dt) because the potential barrier is simply the function of total trap state number. On the other hand, the drain current in the strong inversion region (ID,INV) is not simply the function of WGB × Dt, but more sensitive to the variation of Dt than that of WGB. For example, ID,INV becomes half when Dt increases five times (from 0.2 × 1021 to 2 × 1021 cm-3·eV-1) with WGB × Dt kept constant (WGB reduces from 5 to 1 nm). At the strong inversion region, the higher Dt makes the deeper potential barrier at the center of GB, which reduces ID,INV further. Accordingly, the activation energy of ID,INV also has stronger dependence on Dt as compared to WGB. Finally, it is shown that above mentioned characteristics are available even in the multiple-GB cases when the grain size is twice larger than the GB width.