Design and analysis of memristor based memory cell

Abstract

In recent years, the progression of battery functioned devices has made the low power memory design an urge in the industry. As transistor count increases, the leakage current has made the SRAM unit a power hungry block from both the static and dynamic perspectives. Also the SRAM block is an important part in SOC design nowadays. Here the power dissipation and area are the main factors in designing the memory. SRAM’s are also volatile in nature; they lose what was stored in them if the power is turned off. Memristor is a new circuit device and it can be used forconstructing memory cell. It can be seen that memristance M depends on charge q, which is defined as the time integral of the memristor current. This paper is based on memory cell using memristor. It has the property of non volatileness. It raises the packing density and minmize the power in system on chip (SOC). This concept can help to reducing the leakage power in the memoery element without loss of stored data. SRAM takes large part of power & area, therefore memristor based SRAM is designed to improve power & speed of memory cell. The memristor based memory cell is designed using LT spice EDA tool in 180nm technology. Conventional 6T SRAM cell is modified with memristor and CMOS-Memristor based memory cell is designed and simulated in LT spice for its performance in 180nm technology. Peak and average power are obtained for conventional 6T SRAM cell and proposed memristor memory cell. Power results are compared and shows that power reduction is achieved in memristor based memory cell when compared with conventional 6T SRAM cell. Read and write operation is simulated to evaluate the read time and write time of proposed memory cell.