FPGA implementation of contention free turbo decoder for wireless communications

Abstract

higher data rates were supported by long term evolution (LTE). When there is higher data rates, error detection and correction of the data goes complex. To solve that problem turbo codes are much efficient. By parallelizing the required procession in turbo decoders, effective high rates are achieved and it reaches the channel capacity much better than other codes. In turbo decoder an interleaver plays a crucial role. An interleaver is much preferable for LTE is Quadratic Permutation Polynomial (QPP). It makes the interleaver which is appropriate in parallel decoding. In this paper, a simple Add-compare-select (ACS) network is proposed instead of QPP interleaver which is efficient. The proposed architecture can be used as both interleaver and deinterleaver. The hardware interleaver is used for high speed low complexity. In turbo coding deinterleaver is used. For the proposed interleaver/deinterleaver doesn’t require any memory. The implementation of turbo encoder and turbo decoder is done by a Virtex-6 FPGA and compared the result with QPP interleaver.