A Data Compression Technique for Built-In Self-Test

Abstract

Data compression is often used to reduce the complexity of test data in the area of fault diagnosis in digital systems. A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed and the use of these gates in the design of self-testing and error-propagating space compressors (STEP SC’s) are discussed. It is argued that the data compression technique proposed could reduce the hardware complexity in built-in self-test (BIST) logic design as well as in designs using external tester environments. © 1988 IEEE