L-Shaped Tunnel Field-Effect Transistor-Based 1T DRAM with Improved Read Current Ratio, Retention Time, and Sense Margin

Abstract

In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated through 2-D TCAD simulations. The SiGe storage is utilized to boost not only the sense margin (SM) but also the retention time (RT) in comparison to the previously published TFET-based 1T DRAMs. The simulation results reveal that the LTFET 1T DRAM acquired the SM of $6.2~\mu \text{A}/\mu \text{m}$ with RT of 1.7 s when 50-nm gate length was adopted at 27 °C, whereas at 85 °C, the LTFET 1T DRAM attains the SM and RT of $5.1~\mu \text{A}/\mu \text{m}$ and 290 ms, respectively. Furthermore, the LTFET 1T DRAM still attains the RT of 1.3 s at 27 °C when the gate length is scaled down to 20 nm. Thus, LTFET 1T DRAM exhibits a better gate length scalability in comparison to the counterpart TFET-based 1T DRAMs. In addition, we observed that the impact of ion irradiation on the proposed cell exhibits almost the same SM before and after the ion strike.