Single base modular multiplication for efficient hardware RNS implementations of ECC

Abstract

The paper describes a new RNS modular multiplication algorithm for efficient implementations of ECC over FP. Thanks to the proposition of RNS-friendly Mersenne-like primes, the proposed RNS algorithm requires 2 times less moduli than the state-of-art ones, leading to 4 times less precomputations and about 2 times less operations. FPGA implementations of our algorithm are presented, with area reduced up to 46%, for a time overhead less than 10%.