Multi-Rate Discrete Domain Modeling of Power Hardware-in-The-Loop Setups

Abstract

Power Hardware-in-the-Loop (PHIL) facilitates the testing of novel power engineering solutions in the lab, allowing a flexible testing environment while keeping the high testing fidelity of real hardware. Due to the analog/digital intersection of the PHIL setup, selecting simply continuous or single-rate discrete-time domain fails to model such a hybrid system accurately. This article proposes a multi-rate discrete-time modeling approach of a PHIL setup that can estimate the mixed analog and digital nature of the PHIL accurately, resulting in accuracy improvement over a wide range of frequencies. The proposed approach applies two different sampling times, a large one connected to the digital simulator and a small one for modeling the analog-hardware part. Dynamics and delays of interfaces, such as analog-to-digital converters, the power amplifier, the sensor, and the low-pass filter, have been accurately modeled and validated by means of experimental results.