The status of nanoimprint lithography for high volume semiconductor manufacturing

Abstract

Imprint lithography is an effective and well known technique for replication of nano-scale features. For the purpose of semiconductor device fabrication, nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. In this paper we describe the latest performance update of the equipment, and to discuss the alignment system and overlay methods needed to yield advanced semiconductor devices. Throughputs of up to 90 wafers per hour have been achieved using a cluster system approach. On tests wafers a mix and match overlay of 3.2 nm is demonstrated. Additionally, a Drop Pattern Compensation (DPC) method is introduced as an additional means for improving overlay. Finally, to address cost of ownership, a mask lifetime of over 300 wafer lots has been demonstrated.