Compact Reliability Model of Analog RRAM for Computation-in-Memory Device-to-System Codesign and Benchmark

Abstract

A physics-based compact model of reliability degradation in analog resistive random access memory (RRAM) is developed. The model captures the stochastic degradation behaviors of retention, bit yield, and endurance during analog resistive switching. The model is verified with statistical data measured from analog RRAM arrays. Based on this compact model, a device-to-system simulation framework for the computation-in-memory (CIM) system is developed. This simulation framework is a silicon-verified versatile simulator that supports both inference and training, and fully considers the device nonideal effects and circuit constraints. Based on the reliability evaluation results, optimization guidelines to suppress the impact of device reliability degradation are proposed. This work provides a useful device-system codesign tool for developing large-scale CIM systems with high performance.