Efficient reliability evaluation of combinational and sequential logic circuits

Abstract

Reliability has become one of the major goals for designs based on emerging technologies. Therefore, reliability evaluation should be included in the design flow of logic integrated circuits. In this paper, a probability transfer matrix-based method is developed for reliability evaluation of combinational and sequential logic circuits. The proposed method for combinational circuits is based on correct and incorrect probabilities for the binary logic values (0 and 1) of the nodes of the circuit. In this method, the reconvergent fanouts problem is handled using the concept of correlation coefficients. The reliability evaluation of sequential logic circuits is carried out by first breaking the loops, followed by iterative application of the combinational method on the converted circuit. The accuracy and scalability of the proposed methods are proved by various simulations on ISCAS 85 and LGSynth91 benchmark circuits for the combinational method and on ISCAS 89 benchmark circuits for the sequential method. The results show less than 2 % average error for reliability estimation compared with Monte Carlo (MC) simulations, outperforming state-of-the-art methods in terms of reliability estimation and algorithm runtime.