Impact of body biasing on the retention time of gain‐cell memories

Abstract

Gain‐cell‐based embedded dynamic random‐access memory (DRAMs) are a potential high‐density alternative to mainstream static random‐access memory (SRAM). However, the limited data retention time of these dynamic bitcells results in the need for power‐consuming periodic refresh cycles. This Letter measures the impact of body biasing as a control factor to improve the retention time of a 2 kb memory block, and also examines the distribution of the retention time across the entire gain‐cell array. The concept is demonstrated through silicon measurements of a test chip manufactured in a logic‐compatible 0.18 μm CMOS process. Although there is a large retention time spread across the measured 2 kb gain‐cell array, the minimum, average and maximum retention times are all improved by up to two orders of magnitude when sweeping the body voltage over a range of 375 mV.