Implementation of Asynchronous Pipelines and Its Applications using FPGA

Abstract

Asynchronous designs have interesting features because of absence of the clock signals and it is another option while designing a digital systems. By overcoming the system timing overhead, asynchronous designs works at high speed and it provide high throughput, utilizes the dynamic power, and also provides the elasticity. However, out of several design styles, the most suitable designs for FPGA platforms are bundled data micro pipelines style, the reason behind it is simplicity of control. In this project, we propose pipeline architecture in a bundled data micro pipeline style to implement the asynchronous digital systems by targeting the FPGA devices. The execution of program or software is achieved using FPGA through parallel processing. The design summary of each architecture shows that the design architecture have better throughput by providing more number of input output bond, less delay by reducing the number of look up tables(LUT), and occupy less area by reducing the number of flip-flop's. The designed architecture is applied for UART design in order to increase the throughput and also for FIR filter design to reach the high efficiency.