A novel pipelined carry adder design based on half adder

Abstract

A new design of binary parallel adder circuit is presented in this paper. The pipeline technique is applied to implement a group of a half adder (HA) blocks to architect the proposed adder. The pipelined carry adder (PCA) method is suitable for carrying out the desired adder by using the HA circuits of XOR and AND gates. The applied technique reduces the critical path delay by 27% compared with the ripple carry adder (RCA) and relatively lowers logic gates by 55% compared with the carry look-ahead adder (CLA). The coded design of the proposed circuit is implemented and simulated on the Cyclone IV FPGA kit platform. Results show that the circuit needs a 7.69 η Sec delay time to provide the output values. The suggested PCA circuit is more attractive than the conventional ripple carry adder for future electronic applications.