Trench Etches in Silicon with Controllable Sidewall Angles

Abstract

This paper describes the role of the temperature of the silicon wafer in controlling a deep trench etch sidewall angle and also the etch rate. In addition, we discuss the role of pressure in controlling etch rate and selectivity. This work was performed in a Tegal 1500 Test Bench. The temperature of the wafer could be held fixed as a function of time at any temperature between 20 ~ and 200~ Our chemistry is chloroform, CHC13 with 02 and N2 as additives. We have found that the sidewall angle of the trench (the angle that the sidewall makes with a normal to the wafer surface) could be varied continuously from about 32 ~ at 40~ to 7 ~ at 190~ The Sidewalls are typically planar and relatively smooth. The bottom of the etch becomes increasingly planar as sidewall angle decreases. In order tbr the above processes to occur, there must be a small flow of N2 through the chamber, e.g., 3-5 sccm. Results from the simulation code SAMPLE suggest that the rate of deposi-tion of a material on the etch surface can control sidewall angle. We theorize that a chlorinated hydrocarbon polymer is being deposited, and that the wafer temperature is controlling the rate of deposition of the polymer. In addition to sidewall angle, for zero 02, increasing wafer temperature over the range stated above can cause the etch rate to increase with increasing temperature by 1800 A/min at a nominal etch rate of 4000 A/min. By adding 10% O~ to the gas mixture, the etch rate becomes insensitive to temperature. By increasing the total gas pressure to 1.2 torr, an etch rate of 8000 A/min has been obtained, with an attendant selectivity in excess of 15. Deep trenches in silicon have several important applications , such as device isolation and trench capacitors. For both applications, a trench that has a depth of two to several micrometers (~m) and a width which can be submi-cron to several micrometers is required. The sidewall profile of the trench is a critical characteristic because it can determine the success of these applications. Deep trench isolation technology has been demonstrated to improve the device performance and integration density in bipolar devices (1, 2) and bulk CMOS devices (3). Trench isolation has several advantages. First, trench isolation reduces the width of the isolation region significantly due to its vertical wall. Second, the deep trench reduces the lateral NPN parasitic transistor gain and thus reduces susceptibility to latchup for a given n to p spacing. Finally, trench isolation gives higher packing density for the same latchup performance since the trench width is about 1 ~m in comparison to the minimum 8 ~m spacing required for conventional LOCOS isolation (4). Morie et al. (5) obtained a depletion capacitor by using CBrF3 gas at a pressure of 15 mtorr to etch a trench 0.6 ~m wide and more than 1.5 p.m deep. Then the trench was refilled with a polysilicon layer on top of 250-300A of oxide. A capacitance of more than 40 fF was obtained for a cell size less than 35 ~m 2. Arai (6) has reported that for a cell size of 85 ~m 2, and using 15 nm of SIO2, a doped face trench capacitor with a capacitance of 23 fF was obtained for zero trench depth; for 3 ~m trench depth, the other quantities being the same, 70 fF was obtained. In this paper, we discuss work which has been done to construct deep trenches with the attributes which make them particularly applicable to the two applications discussed above: a sidewall angle which is fully controllable since it has been shown (7) that filling the trench without a void forming depends on the sidewall angle; planar side-walls which are relatively smooth; a planar trench bottom with a rounded corner at a junction of the bottom and a sidewall; etch rate and selectivity which are acceptable in a manufacturing environment. ~Present address: VLSI Technology, Inc., San Jose, California. 2present address: IBM East Fishkill, Hopewell Junction, New York. We will emphasize the importance of controlling the wafer temperature. For example, we will show that trench sidewall angle is a sensitive function of wafer temperature. To a lesser extent, etch rate and selectivity are also effected by this parameter. For example, the sidewall angle can be varied from 32 ~ to 7 ~ by changing the wafer temperature from 40 ~ to 190~ respectively. Etch rate can be increased by 1800 A/min as temperature of the wafer is varied over the same range. Finally, we will show that etch rate is a sensitive function of total gas pressure. By changing the total gas pressure from 300 to 1.2 torr, the etch rate will increase from 3000 to 8000 ,h./min. The selectivity at the latter pressure exceeds 15. In the next section, we define trench parameters. In the following sections we discuss: equipment used; work we have done in computer simulating our trench etches, and physical mechanisms the simulation suggests; a quantitative study of the temperature dependence of sidewall angle; and, the parameters which affect etch rate and se-lectivity. The final section is a summary and discussion of the paper. Trench profile.-A sketch of the trench profile that we wish to achieve is shown in Fig. 1; it is characterized by a width a, depth h, and sidewall angle 0, measured with respect to the normal to the wafer surface. It is highly desirable that these three parameters should remain independently controllable. For the process that we have developed, we will show that this is the case. For our process, the width at the top of the etch, a, is determined by and is nearly identical with the width of the window in the mask, i.e., the mask line width. This parameter remains fixed during the etch time. As we have stated above, the sidewall angle 0 is an extremely sensitive function of the wafer temperature. The etch depth is sensitive to the total gas pressure and, of course, the etch time. It is a weak function of wafer temperature. A scanning electron micrograph (SEM) of a trench which looks similar to the sketch in Fig. 1 is shown in Fig. 2a. Notice that the sidewalls and trench bottom are planar, and that these surfaces are relatively smooth.) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redistribution subject to ECS terms of use (see 192.88.158.246 Downloaded on 2016-10-27 to IP