Error compensation algorithm for SRF-PLL in three-phase grid-connected converters

Abstract

This paper proposes an error compensation algorithm based on synchronous reference frame phase-locked loop for accurate phase estimation of the distorted three-phase voltages including asymmetrical phase voltages, harmonics, and dc offset. These errors cause undesirable periodic ripples with grid frequency in the traditional PLL and significantly degrade the overall performance of the grid-connected converters. In this paper, the effects of the errors are comprehensively analyzed in the stationary and synchronous reference frames. In particular, the errors are estimated and compensated by controlling the α-axis and β-axis components in a PLL to be balanced. The proposed compensation algorithm can be implemented by some integral operations followed by simple Integral-controllers. The performance and robustness of proposed compensation technique are investigated under distorted grid conditions. The proposed technique is numerically and experimentally verified using Matlab/Simulink and Dspace1202 control board platform.