Hardware architecture for FPGA implementation of a neural network and its application in images processing

Abstract

This work describes a hardware architecture implementation of an associative memory neural network (AMNN) using reconfigurable hardware devices such as FPGA (Field Programmable Gates Arrays) and its applications in image pattern recognition systems. An associative memory is a content-addressable structure that maps specific input representations to specific output representations. It is a system that "associates" two patterns (X, Y) such that when one is encountered, the other can be recalled. In the design, learning and recognizing algorithms for the neural network are implemented by using VHSIC Hardware Description Language. FPGA is used for implementation because they can reduce development time greatly, ease of fast reprogramming, low price, flexible architecture and permitting fast and non expensive implementation of the whole system. The architecture was evaluated as image recognizing system. Likewise, it was necessary to implement and acquisition stage. © 2008 IEEE.