Impact of temperature and interface trapped charges variation on the Analog/RF and linearity of vertically extended drain double gate Si0.5Ge0.5 source tunnel FET

Abstract

This work analyses the reliability issues of vertically extended drain double gate Si1−xGex source tunnel FET on the basis of temperature effect and interface charge effects. The increase in operating temperature increases leakage current because of dominant Shockley-Read-Hall (SRH) recombination at low gate bias leading to degradation in ION/IOFF ratio. Further, the presence of interface trap charges leads to variation in flat band voltage and gate control and thus it effects the device performance. Positive interface trap charges enhance device performance whereas negative interface trap charges degrade device performance. The effect of temperature variation and interface trap charge polarity variation has been studied on device analog/RF and linearity parameters.