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A high density NAND EEPROM with block-page programming for microcomputer applications

Proceedings of the Custom Integrated Circuits Conference (1989)
DOI: 10.1109/CICC.1989.56726
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Abstract

A 5V-only CMOS 4Mb NAND EEPROM with high-speed block-page programming circuits and on-chip test circuits for evaluating the NAND structured cell is described. This high density EEPROM has successfully demonstrated the applicability of these techniques for microcomputer applications which require a large non-volatile memory system with low power consumption. © 1989 IEEE.

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APA

Momodomi, M., Iwata, Y., Tanaka, T., Itoh, Y., Shirota, R., & Masuoka, F. (1989). A high density NAND EEPROM with block-page programming for microcomputer applications. In Proceedings of the Custom Integrated Circuits Conference. https://doi.org/10.1109/CICC.1989.56726

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