Data flow partitioning for clock period and latency minimization

Abstract

We propose an efficient performance-driven two-way partitioning algorithm to take into account clock cycle period and latency with retiming. We model the problem with a Quadratic Programming formulation to minimize the crossing edge count with nonlinear timing constraints. By using Lagrangian Approach on Modular Partitioning (LAMP), we merge nonlinear constraints to the objective function. The problem is then decomposed into primal and dual two subprograms. The primal and dual problems are solved by a Quadratic Boolean Programming approach and by a subgradient method using cycle mean method, respectively. Experimental results show our algorithm achieves an average of 23.35% clock cycle period and 19.54% latency reductions compared to the Fiduccia-Mattheyses algorithm. In terms of the average number of the crossing edges, our results are only 1.85% more.