Design and Implementation of Vlsi Architecture for Arrhythmia Detection

Abstract

Arrhythmia is one in all the foremost well-liked heart diseases that might result in serious consequences. In case of arrhythmia, the heart rate may be either too fast or slow. When a person suffers from arrhythmic the heart may not pump sufficient blood to all body parts that is necessary for circulation. some of the symptoms of arrhythmia includes faintness ,fluttering your chest, a light headedness or dizziness, fainting or near fainting and on the worst it may turn out to be deadly causing ventricular fibrillation. Due to this it is very crutial to detect conditions of arrhythmia. It is very difficult to identify the symptoms of arrhythmia from a long ECG record. This projects presents a VLSI based design of high speed and minimum area for arrhythmia detection .It uses arithmetic distribution discrete wavelet transform for arrhythmia detection of QRS wave and is implemented using CADENCE. The purpose of distributive arithmetic discrete wavelet change is to compress the ECG signal. ECG signals are generated via MATLAB. The resultant of these coefficients are given to the LUT, which comprises of MIT-BIH databases. Our aim is to detect the QRS complex in the ECG signal and to identify the time and frequency variations. By comparing these variations with that of the reference variations produced in the normal ECG waveform it is easy to identify whether the patient is suffering from arrhythmia or not. The coding was written in verilog and stimulated in modelsim software and implemented using CADENCE tool.