Design and implementation of a new routing algorithm for fault tolerance in network

Abstract

The possibility to integrate more and more cores on the same chip puts severe constraints on the reliability, to which it is important to provide correct services in the presence of faults. Many fault tolerant routing algorithms are used to overcome the faults in Network on chip. However, these routing algorithms, suffer from another problem like the congestion. In this work, a novel approach inspired by Catnap is proposed for NoCs using Local and Global congestion detection mechanisms with hierarchical sub-networks architecture. With the help of these two techniques, the NoC becomes fault tolerant and is able to efficiently utilize the throughput.After simulation results shows that the proposed algorithm gives a better performance by reducing the latency and increase the reliability of the network. In addition, the algorithm has another advantage: it reduces the congestion which is considered as a temporary fault. Simulations show that our proposed algorithm reduces the latency more than 15% and throughput is improved by 20% compared to the PDA-FTR routing.