(Invited) Dielectrics for Graphene Transistors for Emerging Integrated Circuits

Abstract

In this work, we present the use of high- k dielectric material in designing a novel structure of graphene nanoribbon field-effect transistor (GNR FET) to reduce short channel effects (SCE) for emerging integrated circuits. We have also studied influence of high- k dielectric on ON-state current density, threshold voltage and subthreshold slope of GNR tunneling field effect transistors (TFET). In the GNR FET structure, two side metal gates with lower work function than the main gate on top of the silicon dioxide (SiO 2 ) and hafnium oxide (HfO 2 ) insulating layers are used in a conventional double-gate (DG) GNR FET topology to provide virtual extensions to source and drain regions while these are fixed biased and independent of the main gate bias. We have found that the application of HfO 2 in combination with SiO 2 in the proposed GNR FET not only shifts the drain source leakage current to the lower values by several orders of magnitude but also makes the leakage current sensitive to the proportionality of thicknesses of SiO 2 and HfO 2 layers. This improvement makes the structure a more suitable configuration than the typical GNR FET for the integrated circuit design. In GNR TFET structure, SiO 2 , Al 2 O 3 and HfO 2 are considered as dielectric material and their corresponding effects on transistor are studied. By changing dielectric parameters the oxide capacitance changes, followed by the change in threshold voltage. With semi-classical current transport model such variations are closely observed for the proposed GNR TFET model.