Effect of Temperature on Single Event Latchup Sensitivity

Abstract

Single-Event Latchup (SEL) concerns CMOS technology as a major reliability issue and it is influenced by different parameters. In this work, the effect of the temperature variation on SEL has been investigated and its effect has been analyzed combining the variation of three parameters related to the geometry and to the design of the component: doping profile, anode to cathode spacing (A-C spacing) and substrate and well taps placement. 2D TCAD simulations have been performed, using an NPNP structure based on 65nm CMOS inverter. From these simulations, we have analyzed threshold LET and SEL rate. Results show that temperature impact is stronger when the component is less sensitive to SEL.