Consummation and contrastive analysis of digital modulation schemes using cell based design

Abstract

The rapid growth and fast approaching advancement in the communication technology has led to rapid increase in usage of digital communication technology over analog communication technology resulted in the process of passing information more securely from one to another. Advancement of technology resulted in cost effective SOC’s utilized in designing a well implemented QPSK modulator with booth multiplier as an integral part of the design. This project deals with the critical parametric problems involved in technologies like cell sizing, timing constraints. The main criterion involved here is the usage of the IP cell based design as a subset of the communication system design. The progression of the design is evaluated in the Verilog compiler with the help of an IP integrator present in XILINX VIVADO 14.2. Basic HDL is used for its prior simulation in Xilinx RTL simulator. The main advantage of the design is the re usage of the modulator without writing and simulating the HDL code. The obtained design can be compared with other methods of modulations such as BASK, BPSK, BFSK in terms of critical parametric issues and then it is simulated that can obtain better results with high accuracy.