Run-time FPGA reconfiguration for power-/cost-optimized real-time systems

Abstract

The paper describes a new approach of a flexible run-time system for handling dynamic function reconfiguration in fine-grain Virtex FPGAs, whereas the fulfillment of given real-time constraints are central. Moreover, the detailed evaluation and measurement of the power consumption situation during this dynamic reconfiguration process is essential for realistically quantifying the power loss of fine-grain FPGAs during dynamic reconfiguration processes. This kind of real-time run-time systems and power analysis give the designer and user the possibility to compare FPGA implementation alternatives and to apply the required functionality reconfigurations during the selected application scenarios. Thus, a qualified decision can be done between fine-grain FPGAs of different sizes and different dynamic reconfiguration frequencies, e.g. using smaller and more cost- as well as power-efficient FPGAs by temporarily outsourcing suitable functionalities. © 2006 International Federation for Information Processing.