VLSI based low power multiply accumulate unit employing kogge stone adder with modified pre-processing and post-processing stages

Abstract

The high demand of low power electronic devices necessitates the implementation of novel power management strategies in wide range of applications including signal processing in biomedical device applications. Digital hearing aid is such a biomedical device that uses a Digital Signal Processor (DSP) with a MAC unit and several filters for faster processing, better acoustic signal capture and better noise rejection. The device is designed to help patients having hearing impairment. The objective of this paper is to implement a Multiply Accumulate (MAC) unit based on a modified Kogge Stone adder (KSA) for a DSP module. The unit is designed using Verilog Hardware Description Language (HDL) and simulated and synthesized using Xilinx Vivado Design Suite 2015.2. The design is synthesized for Artix-7 series Field Programmable Gate Array (FPGA). The analysis showed that the proposed design has significant improvement in the power consumption and the figure of merit. The 16 bit design showed an improvement of 11.29% in the power consumption and 6.18% in the figure of merit.